With the continuous shrinking of the technical nodes of semiconductor technology, the semiconductor technology has gradually transitioned from planar CMOS transistors to three-dimensional fin field-effect transistors (FinFETs). In a FinFET, the gate structure is able to control the channel region from at least two sides. Thus, comparing with the planar MOSFET, the FinFET has a significantly higher control ability to the channel region. Accordingly, the FinFET is able to effectively inhibit the short-channel effect, etc. Further, the FinFET has a desired compatibility with the existing fabrication techniques of integrated circuits (ICs).
FIGS. 1-2 illustrate an existing fabrication process of a FinFET. As shown in FIGS. 1-2, the process includes providing a semiconductor substrate 10; and forming a plurality of fins 11 on the semiconductor substrate 10. Specifically, the semiconductor substrate 10 includes a silicon substrate 101 having at least two discrete protruding structures (not labeled), and an insulation layer 102 formed between the protruding structures. The top surface of the insulation layer 102 is lower than the top surfaces of the protruding structures. The portions of the protruding structures higher than the top surface of the insulation layer 102 are configured as the fins 11.
Further, the process also includes forming a gate structure 12 crossing over the fins 11. The gate structure 12 includes a gate oxide layer 121 and a gate electrode layer 122 formed on the gate oxide layer 121.
Further, referring to FIG. 2, the process also includes performing a lightly-doped drain (LDD) ion implantation process on the two sides of the fins 11 to form LDD ion implanting regions. Each of the fins 11 includes a first side surface 111 and a second side surface 112 facing the first side surface 111 of an adjacent fin. The LDD ion implantation process is performed on the first side surfaces 111 of the fins 11 first; and then performed on the second side surfaces 112 of the fins 11. The doping ions of the LDD ion implantation process are phosphorus ions.
Further, the process also includes forming a silicon carbide layer (not shown) on the surface of the fins 11 at both sides of the gate structure 12. The silicon carbide layer is formed by an in-situ doping growth process. That is, the silicon carbide layer is doped with source and drain doping ions. Thus, the source region and the drain region of the N-type FinFET are formed. The source and drain doping ions are phosphorus ions.
Further, a silicon cap (Si Cap) layer is formed on the silicon carbide layer; and a metal layer is formed on the Si Cap layer. A thermal annealing process is performed on the metal layer; and the metal layer and Si Cap are melted together to form a metal silicide layer.
However, the performance of the N-type FinFETs formed by the existing techniques may be unable to match the desired requirements. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.